specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. d1208 ms 20080356-s00007 no.a1159-1/7 lv5050nv overview the lv5050nv is a high efficiency dc/dc converter controller ic adopting a synchronous rectifying system. incorporating numerous functions on a single chip with easy external setting, it can be used for a wide variety of applications. this device is optimal for use in internal power supply systems which are used in electronic devices, lcd-tvs, dvd recorders, etc. functions ? step-down dc/dc converter controller with 1-channel ? input uvlo circuit, ? built-in over current detection function ? built-in soft-start/soft-stop function ? built-in start-up delay circuit ? built-in output voltage monitor function (under vo ltage protection with power good and timer latch) ? synchronized operation is possible between different devices. specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage v in 18 v allowable power dissipation pd max mounted on a specified board* 800 mw junction temperature tj 150 c operating temperature topr -20 to 85 c storage temperature tstg -55 to +150 c * specified board: 114.3mm 76.1mm 1.6 mm, glass epoxy board. continued on next page. bi-cmos ic dc / dc converter controller orderin g numbe r : ena1159
lv5050nv no.a1159-2/7 continued from preceding page. parameter symbol conditions ratings unit allowable terminal voltage *2 1 hdrv,cboot 28 v 2 between hdrv, cboot and sw 6.5 v 3 v in , ilim, rsns, sw, pgood 18 v 4 vlin5, v dd , ldrv 6.5 v 5 comp, fb, ss, uv_delay td, ct, clko vlin5+0.3 v *2: the allowable terminal voltage, the sgnd+pgnd pin becomes a st andard except for no.2 of the allowable terminal voltage abou t no.2 of the allowable terminal voltage, t he sw pin becomes a standard. recommended operating condition at ta = 25 c parameter symbol conditions ratings unit supply voltage v in v in and vlin5 pins opens 7.5 to 16 v supply voltage v in v in and vlin5 pins shorted 4.5 to 6.0 v electrical characteristics at ta = 25 c, v in =12v, unless especially specified ratings parameter symbol conditions min typ max unit system reference voltage for comparing v ref 0.818 0.826 0.834 v supply current 1 i cc 1 td = 5v (except for the ciss charge) 2 4 ma supply current 2 i cc 2 td = 0v 0.3 0.6 1.2 ma 5v supply voltage vlin5 i vin 5 = 0 to 10ma 4.75 5.00 5.25 v over-current sense comparator offset v cl os -5 +5 mv over-current sense reference current source i cl v in = 10 to 14v 7.47 8.30 9.13 a leading edge pulse blank time tlepb 120 150 soft start source current i ss sc td = 5v -2.0 -3.5 -5.0 a soft start sink current i ss sk td = 0v 0.5 2.0 ma soft start clamp voltage v ss t0 when the voltage of the ss pin operating 1.2 1.6 2.0 v uv_delay source current i sc uvd uv_delay = 2v -6.1 -8.6 -12.0 a uv_delay sink current i sk uvd uv_delay = 2v 0.5 2 ma uv_delay threshold voltage vuvd 1.9 2.4 3.0 v uv_delay operating voltage vuvp 100% at v fb = v ref 87 92 97 % vuvp detection hysteresis ? vuvp 1.5 % output discharge transistor on resistance v sw on 5 10 20 ? output part cboot leakage current icboot v cboot = vsw + 6.5v 10 a hdrv ldrv source current i sc drv 0.5 1.0 a hdrv ldrv sink current i sk drv 0.5 1.0 a hdrv lower on resistance r h drv i out = 500ma 0.5 1.5 3.0 ? ldrv lower on resistance r l drv i out = 500ma 0.5 1.5 3.0 ? synchronous on prevention dead time 1 t dead 1 ldrv off hdrv on 50 70 120 ns synchronous on prevention dead time 2 t dead 2 hdrv off ldrv on 70 120 280 ns oscillator oscillation freaquency f osc ct = 130pf 280 330 380 khz oscillation frequency range f osc op 250 1100 khz maximum on duty d on max ct = 130pf 83 90 79 % minimum on time t on min ct = 130pf 100 ns upper-side voltage saw- tooth wave v saw h f osc = 300khz 1.5 2 2.6 v lower-side voltage saw-tooth wave v saw l f osc = 300khz 0.8 1 1.2 v continued on next page.
lv5050nv no.a1159-3/7 continued from preceding page. ratings parameter symbol conditions min typ max unit error amplifier error amplifier input current i fb -190 -100 -50 na comp pin source current i comp sc -150 -100 -50 a comp pin sink current i comp sk 18 100 150 a error amplifier gm gm 500 700 900 umho logic output power good low level source current i pwrgd l v pgood = 0.4v 0.5 1.0 ma power good high level leakage current i pwrgd h v pgood = 12v 10 a power good operation voltage vpwrgd 100% at v fb = v ref 87 92 97 % tp pin threshold voltage v on td when the voltage of the td pin rises 1.5 2.4 3.5 v tp pin high impedance voltage v td h when v in and vlin5 pins are set to open 4.5 5.0 5.5 v td pin charge source current i td sc -2.0 -3.5 -5.0 a td pin discharge sink current i td sk 0.2 1.0 ma clko high level voltage v clko h i clko = 1ma 0.7v5lin v clko low level voltage v clko l i clko = 1ma 0.3v5lin v protection function v in uvlo release voltage v uvlo 3.5 4.1 4.3 ma uvlo hysteresis ? v uvlo 0.4 a uvlo released input voltage v in vuvlo 4.8 5.5 6.3 v
lv5050nv no.a1159-4/7 package dimensions unit : mm (typ) 3179c pin assignment 1sw 2hdrv 3cpoot 4vlin5 5rsns 6(nc) 7ilim 8td 20 19 14 13 12 11 9 10 pgnd ldrv uv_delay pgood ct clko ss v in 18 17 16 15 v dd sgnd comp fb lv5050nv top view sanyo : ssop20(225mil) 6.5 4.4 6.4 0.22 0.65 (0.33) 11 0 11 20 0.5 0.15 1.5max 0.1 (1.3) 0 pd max - ta -20 1000 600 200 800 400 20 04060 80 100 416 85 ambient temperature, ta -- c allowable power dissipation, pd max -- mw specified board: 114.3 76.11.6mm 3 glass epoxy board
lv5050nv no.a1159-5/7 block diagram 8.6a r s q q r s q q por uv_delay sgnd vref error amp fb ch1 output comp bg refrrence bg iref vref ilim comp ldrv v dd sw hdrv cboot rsns v in pgnd uv ct clko 0 deg vlin5 por uv_timeout sync. pulse out vref 0.8v ss 3.5a 3.5a td 2.4v sd por ssend 1.6v cont1 pgood ssend 8.6a 2.4v sd 0v 5v 0.87vref uv cont isense amp ilim pwm comp voltage and current generator current bias corrective ramp pwm logic skip control shifter & latch shoot through protection sequencer active discharge rdson= 15? internal bias 5v reg (allways on) 4.2v / 3.8v 0 deg osc 300khz input power supply ch1 output
lv5050nv no.a1159-6/7 pin functions pin no. pin name description 1 sw this pin is connected with the switching node. a source of an external upper side mos-fet and a drain of an external lower side mos-fet are connected with this pin. this pin becomes the return current path of the hdrv pin. this pin is connected with a transistor drain of the discharge mos- fet for soft stop in the ic (typical 15 ? ). also, this pin has the signal output part for the short through prevention of both the upper and lower mos-fets. when this terminal voltage becomes 1v or less for pgnd, the ldrv pin is turned on. 2 hdrv the gate drive pin for an external upper side mos-fet. 3 cboot the bootstrap capacity connection pin. the gate drive power of upper mos-fet is provided by this pin. this pin is connected to the v dd pin through a diode and is connected to the sw pin through the bootstrap capacity. 4 vlin5 the output pin of an internal regulator of 5v. the current is provided by the vin pin. also, power supply of the control circuit in the ic is provided by this pin. connect an output capacitor of 4.7 f between this pin and sgnd. a regulator of 5v operates, even if the ic is in the standby state. this pin is monitored by an uvlo function and t he ic starts by the voltage of 4.0v or more (the ic is off by the vo ltage of 3.8v or less.) 5 rsns the input pin of the over current detecti on comparator / the current detection amplifier to detect resistance, this pin is connected to the under side of a resistor for the current detection between the v in pin and the drain of the upper mos-fet. also, to use the on resistance of mos-fet for the current detection, connect this pin to the source of the upper mos-fet. to prevent the common impedance of main current to the detection-voltage, this pin is connected by independent wiring. 6 nc no connection. 7 ilim the pin to set the trip point for over current detection. since the sink current source of 8.3 a (ilim) is connected in the ic, the over-current detection voltage (ilim rlim) is generated by connecting a resistor rlim between this pin and the v in pin. the over-current is detected by comparing the voltage between the v in pin and the ilim pin to the current detection resistance rsns or both end voltage of the upper mos-fet. 8 td start-up delay pin. the time until the ic starts after releasing por is set by connecting a capacitor between this pin and sgnd. after releasing por, an external capacitor is ch arged up by the constant current source of 3.5 a in the ic. when this terminal voltage becomes 2.4v or more, the ic starts. also, when this terminal voltage becomes 2.4v or less, the ic becomes the standby st ate. if external capacitor is not connected, the ic instantly starts after releasing por. 9 ss the pin to connect a capacitor for soft start. after releasing por, when the voltage of the td pin becomes 2.4v or more, t he ss pin is charged by an internal constant current source of 3.5 a. since this pin is connected to the positive input of the transf ormer conductance amplifier, the ramp-up wave form of the ss pin becomes the ramp-up wave form of the output. during por operations and after the uv_delay time-out, the ss pin is discharged 10 vin power supply pin of the ic 11 clko the clock output pin. the clock that synchronized to the oscillation waveform of the ct pin is output. to synchronize two or more lv5050nvs, the clko pin of the dev ice that becomes a master is connected to the ct pin of the device that becomes a slave. when two or more the devices are synchronized and the start-up timing is changed by using the td pin between each device, the earlie st start-up device is det ermined as the master. 12 ct the pin to connect an external c apacitor for the oscillator. connect a capacitor between this pin and sgnd. when a capacitor of 130pf is connected between this pin and gnd, the oscillation fr equency can be set up by 330khz. also, this pin is applied by an external clock signal. the pwm operation is performed by the frequency of applied clock signal. when an external clock signal is applied, the rectangular wave of 0v in low level and from 3.3v to 5v in high level is applied. the rectangular wave source needs the fan-out of 1ma or more. 13 pgood the power good pin. the open drain mos-fet of the withstand of 28v is connected in the ic. when the output voltage of channel 1 is less than -13% for the setup voltage, the low level is output. this pin has hysteresis of about (v ref 1.5%). continued on next page.
lv5050nv ps no.a1159-7/7 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. continued from preceding page. pin no. pin name description 14 uv_delay uvp delay pin by connecting a capacitor between this pin and sgnd, the time un til the ic latches off after detecting the uvp state can be set. also, after channel 1 terminated the soft-start function , when the output voltage becomes -80% or less for the setup voltage, an external capacitor is charged by the constant current source of 8.6 a in the ic. when this terminal voltage becomes 2.4v or more, the ic is latched off. if an external capacitor is not connected, the ic is instantly latched off after detecting the uvp state. also, when this pin is shorted to gnd, the uv_delay function is not operated. 15 fb feed back input pin. the minus terminal (-) of the trans conductance amplifier is connected. the voltage generated when the output voltage was divi ded by a resistor is input into this pin. the converter operates so that this pin becomes an internal reference voltage (v ref =0.836v). also, this pin is monitored by the comparators uvp and ovp. when the voltage of this pin becomes less than 87% of the set voltage, the pgood pin is low level. a timer of the uv_delay function operates. also, when the voltage of this pin becomes more than 117% of the set voltage, the ic latches off. 16 comp the pin to connect a capacitor and a resistor for phase compensation. the output of an internal transforme r conductance amplifier is connected. connect an external phase compensation circuit between this pin and sgnd. 17 sgnd the system ground of the ic. the refer ence voltage is generated based on this pin. this pin is connected to the power supply system ground. 18 v dd power supply pin for the gate drive of an external lower-side mos-fet. this pin is connected to the vlin5 pin through a filter. 19 ldrv the gate drive pin of an external lower-side mos-fet. this pin has the signal input part for prevention of short-through of both the upper and lower mos-fets. when the voltage of this pin becomes less than 1v, the hdrv pin is turned on. 20 pgnd power ground pin. this pin becomes the return current path of the ldrv pin. this catalog provides information as of december, 2008. specifications and inform ation herein are subject to change without notice.
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